The present invention relates generally to phase change memory cells, and more specifically, to a planarization stop layer for forming a phase change memory device.
Phase change material (PCM) has a variety of applications in microelectronic devices such as optical storage media and solid state phase change memory devices. Phase change random access memory (PRAM) devices, for example, store data using a phase change material, such as, for example, a chalcogenide alloy, that transforms into a crystalline state or an amorphous state during cooling after a heat treatment. Each state of the phase change material has different resistance characteristics. Specifically, the phase change material in the crystalline state has low resistance and the phase change material in the amorphous state has high resistance. The crystalline state is typically referred to as a “set state” having a logic level “0”, and the amorphous state is typically referred to as a “reset state” having a logic level “1”. A current passed through the phase change material creates ohmic heating and causes the phase change material to melt. Melting and gradually cooling down the phase change material allows time for the phase change material to form the crystalline state. Melting and abruptly cooling the phase change material quenches the phase change material into the amorphous state.
Pore integration provides a uniform and sub-lithographic patterning for PCM application. Conventionally, a key hole method is performed to form a pore within phase change memory cell. FIG. 1 illustrates a conventional key hole method. In FIG. 1, a substrate 10 including a bottom electrode 12 is provided. A first dielectric layer 14 is formed on the substrate 10, an isolation layer 16 is formed on the first dielectric layer 14, and a second dielectric layer 18 is formed on the isolation layer 16. A photo resist layer (not shown) is formed over the second dielectric layer 18. A via 20 is formed to extend to the first dielectric layer 14. Next, the photo resist layer is removed and the isolation layer 16 is recessed, creating overhang portions of the second dielectric layer 18. A conformal film 22 e.g., an amorphous silicon layer is deposited within the via 20 and pinched to form a void (i.e., a keyhole 24) in the via 20. Typically, the conformal film 22 is recessed and the keyhole 24 is transferred down into the first dielectric layer 16 by a reactive ion etching (RIE) operation, to form a pore. There are variations in center to edge thickness of the conformal film 22 due to the nature of the process. The difference in the conformal film 22 thickness can be coupled into the pore diameter and depth formed during the RIE process, causing the CD variation. A planarization operation e.g., a silicon chemical mechanical polishing (CMP) operation is typically used to attempt to improve the uniformity across the wafer prior to the performance of the RIE process. However, when the CMP operation is performed it may cause a tip 24a of the key hole 24 to open, thereby causing CMP slurry to get into the key hole 24 and block the RIE process for transferring the key hole 24 to the first dielectric layer 14 to form the pore.